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N64S818HA
READ Status Register Instruction (RDSR)
This instruction provides the ability to read the Status
register. The register may be read at any time by performing
CS
the following timing sequence. Bits 0, 6 and 7 contain the
data for the functional operation and Bit 1 will read data type
‘1’ for the 64 Kb device.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Status Register Data Out
SO
High ? Z
7
6
5
4
3
2
1
0
Figure 16. READ Status Register Instruction (RDSR)
Bit 7
Mode
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
1 = 64 Kb
Bit 0
Hold Function
0
1
0
1
0 = Word Mode
0 = Page Mode
1 = Burst Mode
1 = Reserved
Figure 17. Status Register
0 = Hold
1 = No Hold
Power ? Up State
The serial SRAM enters a know state at power ? up time. The device is in low ? power standby state with CS = 1. A low level
on CS is required to enter an active state.
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